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1 features ? fast read access time ? 90 ns 5-volt only reprogramming sector program operation ? single cycle reprogram (erase and program) ? 2048 sectors (256 bytes/sector) ? internal address and data latches for 256 bytes internal program control and timer hardware and software data protection two 16k bytes boot blocks with lockout fastsectorprogramcycletime?10ms data polling for end of program detection low power dissipation ? 40maactivecurrent ? 100 a cmos standby current typical endurance > 10,000 cycles single 5v 10% supply cmos and ttl compatible inputs and outputs description the AT29C040A is a 5-volt only in-system flash programmable and erasable read only memory (perom). its 4 megabits of memory is organized as 524,288 words by 8 bits. manufactured with atmel?s advanced nonvolatile cmos eeprom technology, the device offers access times up to 90 ns, and a low 220 mw power dissipation. when the device is deselected, the cmos standby current is less than 100 a. the device endurance is such that any sector can typically be written to in excess of 10,000 times. the programming algorithm is compatible with other devices in atmel?s 5-volt only flash family. 4-megabit (512k x 8) 5-volt only 256-byte sector flash memory AT29C040A rev. 0333i?flash?05/02 dip top view pin configurations pin name function a0 - a18 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a17 a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 plcc top view tsop top view ? type 1 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a12 a15 a16 a18 vcc we a17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 a17 we vcc a18 a16 a15 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3
2 AT29C040A 0333i ? flash ? 05/02 to allow for simple in-system reprogrammability, the AT29C040A does not require high input voltages for programming. five-volt-only commands determine the operation of the device. reading data out of the device is similar to reading from an eprom. reprogramming the AT29C040A is performed on a sector basis; 256 bytes of data are loaded into the device and then simultaneously programmed. during a reprogram cycle, the address locations and 256 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. the end of a program cycle can be detected by data polling of i/o7. once the end of a program cycle has been detected, a new access for a read or program can begin. block diagram device operation read: the AT29C040A is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention. byte load: byte loads are used to enter the 256 bytes of a sector to be programmed or the software codes for data protection. a byte load is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . program: the device is reprogrammed on a sector basis. if a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. any byte that is not loaded during the programming of its sector will be erased to read ffh. once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. after the first data byte has been loaded into the device, successive bytes are entered in the same manner. each new byte to be programmed must have its high to low transition on we (or ce ) within 150 s of the low to high transition of we (or ce )ofthe preceding byte. if a high to low transition is not detected within 150 s of the last low to high transition, the load period will end and the internal programming period will start. a8 to a18 specify the sector address. the sector address must be valid during each high to low transition of we (or ce ). a0 to a7 specify the byte address within the sector. the bytes may be loaded in any order; sequential loading is not required. once a programming operation has been initi- ated, and for the duration of t wc , a read operation will effectively be a polling operation.
3 AT29C040A 0333i ? flash ? 05/02 software data protection: a software controlled data protection feature is avail- able on the AT29C040A. once the software protection is enabled a software algorithm must be issued to the device before a program may be performed. the software protection feature may be enabled or disabled by the user; when shipped from atmel, the software data protec- tion feature is disabled. to enable the software data protection, a series of three program commands to specific addresses with specific data must be performed. after the software data protection is enabled the same three program commands must begin each program cycle in order for the programs to occur. all software program commands must obey the sector pro- gram timing specifications. the sdp feature protects all sectors, not just a single sector. once set, the software data protection feature remains active unless its disable command is issued. power transitions will not reset the software data protection feature, however the software fea- ture will guard against inadvertent program cycles during power transitions. after setting sdp, any attempt to write to the device without the three-byte command sequence will start the internal write timers. no data will be written to the device; however, for the duration of t wc , a read operation will effectively be a polling operation. after the software data protection ? s 3-byte command code is given, a byte load is performed by applying a low pulse on the we or ce input with ce or we low (respectively) and oe high. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . the 256 bytes of data must be loaded into each sector by the same procedure as outlined in the program section under device operation. hardware data protection: hardware features protect against inadvertent pro- grams to the AT29C040A in the following ways: (a) v cc sense ? if v cc is below 3.8v (typical), the program function is inhibited; (b) v cc power on delay ? once v cc has reached the v cc sense level, the device will automatically time out 5 ms (typical) before programming; (c) pro- gram inhibit ? holding any one of oe low, ce high or we high inhibits program cycles; and (d) noise filter ? pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a pro- gram cycle. product identification: the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the atmel product. in addition, users may wish to use the software product identi- fication mode to identify the part (i.e. using the device code), and have the system software use the appropriate sector size for program operations. in this manner, the user can have a common board design for 256k to 4-megabit densities and, with each density ? ssectorsizein a memory map, have the system software apply the appropriate sector size. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. data polling: the AT29C040A features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the com- plement of the loaded data on i/o7. once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data polling the AT29C040A provides another method for determining the end of a program or erase cycle. during a program or erase operation, suc- cessive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. optional chip erase mode: the entire device can be erased by using a 6-byte soft- ware code. please see software chip erase application note for details.
4 AT29C040A 0333i ? flash ? 05/02 boot block programming lockout: the AT29C040A has two designated memory blocks that have a programming lockout feature. this feature prevents programming of data in the designated block once the feature has been enabled. each of these blocks consists of 16k bytes; the programming lockout feature can be set independently for either block. while the lockout feature does not have to be activated, it can be activated for either or both blocks. these two 16k memory sections are referred to as boot blocks . secure code which will bring up a system can be contained in a boot block. the AT29C040A blocks are located in the first 16k bytes of memory and the last 16k bytes of memory. the boot block programming lockout feature can therefore support systems that boot from the lower addresses of memory or the higher addresses. once the programming lockout feature has been activated, the data in that block can no longer be erased or programmed; data in other memory locations can still be changed through the regular programming methods. to activate the lockout feature, a series of seven program commands to specific addresses with specific data must be performed. please see boot block lockout feature enable algorithm. if the boot block lockout feature has been activated on either block, the chip erase function will be disabled. boot block lockout detection: a software method is available to determine whether programming of either boot block section is locked out. see software product identifi- cation entry and exit sections. when the device is in the software product identification mode, a read from location 00002h will show if programming the lower address boot block is locked out while reading location 7fff2h will do so for the upper boot block. if the data is fe, the cor- responding block can be programmed; if the data is ff, the program lockout feature has been activated and the corresponding block cannot be programmed. the software product identifi- cation exit mode should be used to return to standard operation. absolute maximum ratings* temperature under bias ................................ -55 cto+125 c *notice: stresses beyond those listed under ? absolute maximum ratings ? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 cto+150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc +0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
5 AT29C040A 0333i ? flash ? 05/02 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1f, device code: a4. 5. see details under software product identification entry/exit. dc and ac operating range AT29C040A-90 AT29C040A-12 AT29C040A-15 AT29C040A-20 operating temperature (case) com. 0 c-70 c0 c-70 c0 c-70 c 0 c-70 c ind. -40 c-85 c-40 c-85 c-40 c-85 c -40 c-85 c v cc power supply 5v 10% 5v 10% 5v 10% 5v 10% note: not recommended for new designs. operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in standby/write inhibit v ih x (1) xxhighz program inhibit x x v ih program inhibit x v il x output disable x v ih xhighz product identification hardware v il v il v ih a1 - a18 = v il ,a9=v h , (3) a0 = v il manufacturer code (4) a1 - a18 = v il ,a9=v h , (3) a0 = v ih device code (4) software (5) a0 = v il manufacturer code (4) a0 = v ih device code (4) dc characteristics symbol parameter condition min max units i li input load current v in =0vtov cc 10 a i lo output leakage current v i/o =0vtov cc 10 a i sb1 v cc standby current cmos ce =v cc -0.3vtov cc com. 100 a ind. 300 a i sb2 v cc standby current ttl ce =2.0vtov cc 3ma i cc v cc active current f = 5 mhz; i out = 0 ma 40 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol =2.1ma 0.45 v v oh1 output high voltage i oh =-400a 2.4 v v oh2 output high voltage cmos i oh =-100a;v cc =4.5v 4.2 v
6 AT29C040A 0333i ? flash ? 05/02 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc -t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce -t oe after the falling edge of ce without impact on t ce or by t acc -t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter AT29C040A-90 AT29C040A-12 AT29C040A-15 AT29C040A-20 units min max min max min max min max t acc address to output delay 90 120 150 200 ns t ce (1) ce to output delay 90 120 150 200 ns t oe (2) oe to output delay 0 40 0 50 0 70 0 80 ns t df (3)(4) ce or oe to output float 0 25 0 30 0 40 0 50 ns t oh output hold from oe ,ce or address, whichever occurred first 000 0 ns note: not recommended for new designs.
7 AT29C040A 0333i ? flash ? 05/02 input test waveforms and measurement level output test load note: 1. this parameter is characterized and is not 100% tested. t r ,t f <5ns pin capacitance f=1mhz,t=25 c (1) symbol typ max units conditions c in 46pfv in =0v c out 812pfv out =0v
8 AT29C040A 0333i ? flash ? 05/02 ac byte load waveforms (1) we controlled ce controlled note: 1. a complete sector (256 bytes) should be loaded using the waveforms shown in these byte load waveform diagrams. ac byte load characteristics symbol parameter min max units t as ,t oes address, oe setup time 10 ns t ah address hold time 50 ns t cs chip select setup time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )90ns t ds data setup time 50 ns t dh ,t oeh data, oe hold time 10 ns t wph write pulse width high 100 ns
9 AT29C040A 0333i ? flash ? 05/02 program cycle waveforms (1)(2)(3) notes: 1. a8 through a18 must specify the sector address during each high to low transition of we (or ce ). 2. oe must be high only when we and ce are both low. 3. all bytes that are not loaded within the sector being programmed will be indeterminate. program cycle characteristics symbol parameter min max units t wc writecycletime 10 ms t as address setup time 10 ns t ah address hold time 50 ns t ds data setup time 50 ns t dh data hold time 10 ns t wp write pulse width 90 ns t blc byte load cycle time 150 s t wph write pulse width high 100 ns
10 AT29C040A 0333i ? flash ? 05/02 software data protection enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. data protect state will be activated at end of program cycle. 3. data protect state will be deactivated at end of program period. 4. 256 bytes of data must be loaded. load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data to page (256 bytes) (4) writes enabled enter data protect state (2) software data protection disable algorithm (1) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 20 to address 5555 load data to page (256 bytes) (4) exit data protect state (3) software protected program cycle waveform (1)(2)(3) notes: 1. a8 through a18 must specify the sector address during each high to low transition of we (or ce ) after the software code has been entered. 2. oe must be high when we and ce are both low. 3. all bytes that are not loaded within the sector being programmed will be indeterminate.
11 AT29C040A 0333i ? flash ? 05/02 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
12 AT29C040A 0333i ? flash ? 05/02 software product identification entry (1) software product identification exit (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a18 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code is 1f. the device code is a4. load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 pause 10 ms enter product identification mode (2)(3)(5) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 pause 10 ms exit product identification mode (4) boot block lockout feature enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. lockout feature set on lower address boot block. 3. lockout feature set on higher address boot block. load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 load data 00 to address 00000h (2) pause 10 ms load data ff to address 7ffffh (3) pause 10 ms
13 AT29C040A 0333i ? flash ? 05/02 ordering information t acc (ns) i cc (ma) ordering code package operation range active standby 90 40 0.1 AT29C040A-90jc AT29C040A-90pc AT29C040A-90tc 32j 32p6 32t commercial (0 to 70 c) 40 0.3 AT29C040A-90ji AT29C040A-90pi AT29C040A-90ti 32j 32p6 32t industrial (-40 to 85 c) 120 40 0.1 AT29C040A-12jc AT29C040A-12pc AT29C040A-12tc 32j 32p6 32t commercial (0 to 70 c) 40 0.3 AT29C040A-12ji AT29C040A-12pi AT29C040A-12ti 32j 32p6 32t industrial (-40 to 85 c) 150 40 0.1 AT29C040A-15jc AT29C040A-15pc AT29C040A-15tc 32j 32p6 32t commercial (0 to 70 c) 40 0.3 AT29C040A-15ji AT29C040A-15pi AT29C040A-15ti 32j 32p6 32t industrial (-40 to 85 c) 200 40 0.1 AT29C040A-20jc AT29C040A-20pc AT29C040A-20tc 32j 32p6 32t commercial (0 to 70 c) 40 0.3 AT29C040A-20ji AT29C040A-20pi AT29C040A-20ti 32j 32p6 32t industrial (-40 to 85 c) note: not recommended for new designs. package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 32p6 32-lead, 0.600" wide, plastic dual inline package (pdip) 32t 32-lead, thin small outline package (tsop)
14 AT29C040A 0333i ? flash ? 05/02 packaging information 32j?plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 3.556 a1 1.524 2.413 a2 0.381 d 12.319 12.573 d1 11.354 11.506 note 2 d2 9.906 10.922 e 14.859 15.113 e1 13.894 14.046 note 2 e2 12.471 13.487 b 0.660 0.813 b1 0.330 0.533 e 1.270 typ
15 AT29C040A 0333i ? flash ? 05/02 32p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32p6 , 32-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 32p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0 ~ 15 d e eb common dimensions (unit of measure = mm) symbol min nom max note a 4.826 a1 0.381 d 41.783 42.291 note 1 e 15.240 15.875 e1 13.462 13.970 note 1 b 0.356 0.559 b1 1.041 1.651 l 3.048 3.556 c 0.203 0.381 eb 15.494 17.526 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
16 AT29C040A 0333i ? flash ? 05/02 32t ? tsop type 1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32t , 32-lead (8 x 20 mm package) plastic thin small outline package, type i (tsop) b 32t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0 ~ 8 c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation bd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 0.21 e 0.50 basic
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